NeuralBrew

Utilize Logarithmic Number Systems to produce substantially lower energy requirements in AI accelerator chips:

• Replace floating point Graphics Processing Units (GPUs) with Logarithmic Processing Units (LPUs).
• Convert existing backpropagation training algorithms to work with LPUs.
• Transform existing weights and parameters of pre-trained networks such as LLMs and image classifiers for use in LPU chips.

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LPU support for novel algorithm development:

• Maximize utilization of logarithmic identities to greatly reduce energy consumption for calculating statistical parameters of large datasets.
• Produce Energy-based models utilizing contrastive learning.
• Support statistical calculations such as correlations, covariance, cross-entropy, negative log-likelihood, Hessian spectrum, and Brier score log domain calculations.

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Safety and reliability:

• Algorithmic diversity reduces common-mode failures.
• Hardware diversity provides an extra layer of independence.
• Provide support for safety monitoring and critical decision arbitration.

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Develop high performance emulation platform:

• Rapid prototyping of LPU and other novel hardware designs.
• Hardware synthesis from PyTorch and JAX models into FPGA implementations.
• Provide developers with tools to rapidly evaluate algorithm performance at scale.
• Provide energy consumption estimates for ASIC implementations.
• Provide estimates for chip area and memory utilization.
• Selective optimization for power, training times, inference speed and accuracy.

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Provide LPU IP silicon cores:

• Optimize LPU silicon layout for rapid ASIC integration.
• Hardcode weights and parameters in inferece chips to elimate need for memory accesses.
• Integrate with embedded memory cores to improve performance.
• Drop-in replacement for GPU cores.

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Explore novel hardware:

• LPU Integration with compute-in-memory.
• Emulate analog and optical neural networks to evaluate energy and performance.